| addr | bank 0 | addr | bank 1 |
|---|---|---|---|
| 0x00 | Indirect addr | 0x80 | Indirect addr(1) |
| 0x01 | TMR0 | 0x81 | OPTION_REG |
| 0x02 | PCL | 0x82 | PCL |
| 0x03 | STATUS | 0x83 | STATUS |
| 0x04 | FSR | 0x84 | FSR |
| 0x05 | PORTA | 0x85 | TRISA |
| 0x06 | PORTB | 0x86 | TRISB |
| 0x07 | 0x87 | ||
| 0x08 | EEDATA | 0x88 | EECON1 |
| 0x09 | EEADR | 0x89 | EECON2 |
| 0x0A | PCLATH | 0x8A | PCLATH |
| 0x0B | INTCON | 0x8B | INTCON |
| 0x0C ... 0x4F |
General Registers | 0x8C ... 0xCF |
accesses bank 0 |
| 0x50 ... 0x7F |
unimplemented | 0xD0 ... 0xFF |
unimplemented |