- Port B is a 8 bit wide bi-directional port.
- Setting a bit of the TRISB register to 1 will make the corresponding bit of Port B an input.
- Each Port B pin has a weak pull-up. All the weak pull-ups can be disabled by clearing bit 7 of the OPTION register (RBPU).
| Maximum current sourced | 100 mA |
| Maximum current sunk | 150 mA |
Port B Hardware
| Pin | Name | Input | Output | Description |
|---|
| 6 | RB0 | TTL | TTL | Bi-directional I/O Port |
|---|
| INT | ST | - | External Interupt |
| 7 | RB1 | TTL | TTL | Bi-directional I/O Port B |
|---|
| 8 | RB2 | TTL | TTL | Bi-directional I/O Port B |
|---|
| 9 | RB3 | TTL | TTL | Bi-directional I/O Port B |
|---|
| 10 | RB4 | TTL | TTL | Bi-directional I/O Port B, interupt-on-change pin. |
|---|
| 11 | RB5 | TTL | TTL | Bi-directional I/O Port B, interupt-on-change pin. |
|---|
| 12 | RB6 | TTL | TTL | Bi-directional I/O Port B, interupt-on-change pin. |
|---|
| 13 | RB7 | TTL | TTL | Bi-directional I/O Port B, interupt-on-change pin. |
|---|
Port B Register
| Bit | Kind | Name | Description |
Pwr | Other |
| bit 7 | R/W-x | RB7 |
General Purpose I/O bit
1 = pin is > Vih.
0 = pin is < Vil. | x | u |
| bit 6 |
R/W-x | RB6 | x | u |
| bit 5 |
R/W-x | RB5 | x | u |
| bit 4 |
R/W-X | RB4 | x | u |
| bit 3 |
R/W-X | RB3 | x | u |
| bit 2 |
R/W-X | RB2 | x | u |
| bit 1 |
R/W-X | RB1 | x | u |
| bit 0 |
R/W-X | RB0 | x | u |
TRISB Register
| Bit | Kind | Name | Description | Pwr |
Other |
| bit 7 | R/W-1 | TRISB7 | 1 = pin is configured as an input.
0 = pin is configured as an output. | 1 | 1 |
|---|
| bit 6 | R/W-1 | TRISB6 | 1 | 1 |
|---|
| bit 5 | R/W-1 | TRISB5 | 1 | 1 |
|---|
| bit 4 | R/W-1 | TRISB4 | 1 | 1 |
|---|
| bit 3 | R/W-1 | TRISB3 | 1 | 1 |
|---|
| bit 2 | R/W-1 | TRISB2 | 1 | 1 |
|---|
| bit 1 | R/W-1 | TRISB1 | 1 | 1 |
|---|
| bit 0 | R/W-1 | TRISB0 | 1 | 1 |
|---|
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW b'11001111' ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB7-RB6 and RB3-RB0 as inputs
; RB5-RB4 as outputs