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m6800/m6802
condition code register
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bitnamememdescription
7  Always one
6  Always one
5Half carryHset if there was a carry from bit 3 to bit 4 of the result when the result was calculated.
4Interrupt maskIset if the IRQ interrupt is disabled.
3NegativeNset if the most significant bit of the result is set.
2ZeroZset if the result is zero.
1OverflowVset if there was an overflow during last result calculation.
0CarryCset if there was a carry from the bit 7 during last result calculation.
MC6802 - condition code register
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filename:microprocessors - MC6800/MC6802 - condition code register
filename:microprocessors%20%2D%20MC6800%2FMC6802%20%2D%20condition%20code%20register
last edit:March 20 2010 21:11:46 (5172 days ago)
ct = 1716062067.000000 = May 18 2024 15:54:27
ft = 1269133906.000000 = March 20 2010 21:11:46
dt = 446928161.000000