| Opcode | Meaning |
|---|
| org | addr | sets the address the next instruction will be assembled at. |
| end | | signals the end of source. |
Opcodes
| Byte-Oriented File Register Operations |
|---|
| Mnemonic | Description | Function |
|---|
| ADDWF | f,d | Add W and f | (d) := (W) + (f) |
| ANDWF | f,d | AND W and f | (d) := (W) AND (f) |
| CLRF | f | Clear f | (f) := 0 |
| CLRW | | Clear W | W :=0 |
| COMF | f,d | Complement | d := f NOT f |
| DECF | f,d | Decrement | d := f - 1 |
| DECFSZ | f,d | Decrement f, skip if zero | d := f - 1, skip if 0 |
| INCF | f,d | Increment f | d := f + 1 |
| INCFSZ | f,d | Increment f, skip if zero | d := f + 1, skip if 0 |
| IORWF | f,d | Inclusive OR W and f | d := W OR f |
| MOVF | f,d | Move f | d := f |
| MOVWF | f | Move W to f | f := W |
| NOP | | No operation | |
| RLF | f,d | Rotate left f | |
| RRF | f,d | Rotate right f | |
| SUBWF | f,d | Subtract W from f | d := f - W |
| SWAPF | f,d | Swap halves f | f(0:3) ? f(4:7) ? d |
| XORWF | f,d | Exclusive OR W and f | d := W .XOR. f |
| Bit-Oriented File Register Operations |
|---|
| Mnemonic | Description | Function |
|---|
| BCF | f,b | Bit b in register f is cleared | f(b) := 0 |
| BSF | f,b | Bit b in register f is set | f(b) := 1 |
| BTFSC | f,b | test bit b of register f, skip next instruction if clear | skip if f(b) = 0 |
| BTFSS | f,b | test bit b of register f, skip next instruction if set | skip if f(b) = 1 |
| Literal and Control Operations |
|---|
| Mnemonic | Description | Function |
|---|
| ADDLW | kk | Add literal to W | (W) := kk + (W) |
| ANDLW | kk | AND literal and W | (W) := kk AND (W) |
| CALL | kkk | Call subroutine | TOS := PC + 1
PC := kk
PC<12:11> := (PCLATH<4:3>) |
| CLRWDT | | Clear watchdog timer | WDT (and Prescaler if assigned) := 0 |
| GOTO | kkk | Goto address (k is nine bits) | PC(9 bits) := kkk |
| IORLW | kk | Incl. OR literal and W | WREG := kk OR WREG |
| MOVLW | kk | Move Literal to W | WREG := kk |
| OPTION | | Load OPTION register (1) | OPTION Register := WREG |
| RETFIE | | Return from Interrupt | PC := TOS, GIE := 1 |
| RETLW | kk | Return with literal in W | WREG := kk, PC := TOS |
| RETURN | | Return from subroutine | PC := TOS |
| SLEEP | | Go into Standby Mode | WDT := 0, stop oscillator |
| SUBLW | kk | Subtract W from literal | WREG := kk - WREG |
| TRIS | r | Tristate port r (1) | I/O control reg r := WREG |
| XORLW | kk | Exclusive OR literal and W | WREG := kk XOR WREG |
|
f = rgister file address (0x00 to 0x7F)
W = working register (accumulator)
b = bit address within an 8-bit file register
k = literal field, constant data or label
x = don't care location
d = destination select
d = 0: store result in W
d = 1 : store result in f
PC = program counter
TO = time-out bit
PD = power-down bit
|
| ADDWF | f,d | Add W and f | (d) := (W) + (f) |
| ANDWF | f,d | AND W and f | (d) := (W) AND (f) |
| COMF | f,d | Complement | d := f NOT f |
| DECF | f,d | Decrement | d := f - 1 |
| DECFSZ | f,d | Decrement f, skip if zero | d := f - 1, skip if 0 |
| INCF | f,d | Increment f | d := f + 1 |
| INCFSZ | f,d | Increment f, skip if zero | d := f + 1, skip if 0 |
| IORWF | f,d | Inclusive OR W and f | d := W OR f |
| MOVWF | f | Move W to f | f := W |
| SUBWF | f,d | Subtract W from f | d := f - W |
| SUBWF | f,d | Subtract W from f | d := f - W |
| SWAPF | f,d | Swap halves f | f(0:3) ? f(4:7) ? d |
| XORWF | f,d | Exclusive OR W and f | d := W .XOR. f |
| BCF | f,b | Bit b in register f is cleared | f(b) := 0 |
| BSF | f,b | Bit b in register f is set | f(b) := 1 |
| BTFSC | f,b | test bit b of register f, skip next instruction if clear | skip if f(b) = 0 |
| BTFSS | f,b | test bit b of register f, skip next instruction if set | skip if f(b) = 1 |
| ADDLW | kk | Add literal to W | (W) := kk + (W) |
| ANDLW | kk | AND literal and W | (W) := kk AND (W) |
| CALL | kkk | Call subroutine | TOS := PC + 1
PC := kk
PC<12:11> := (PCLATH<4:3>) |
| CLRWDT | | Clear watchdog timer | WDT (and Prescaler if assigned) := 0 |
| GOTO | kkk | Goto address (k is nine bits) | PC(9 bits) := kkk |
| IORLW | kk | Incl. OR literal and W | WREG := kk OR WREG |
| MOVLW | kk | Move Literal to W | WREG := kk |
| OPTION | | Load OPTION register (1) | OPTION Register := WREG |
| RETFIE | | Return from Interrupt | PC := TOS, GIE := 1 |
| RETLW | kk | Return with literal in W | WREG := kk, PC := TOS |
| RETFIE | | Return from Interrupt | PC := TOS, GIE := 1 |
| SLEEP | | Go into Standby Mode | WDT := 0, stop oscillator |
| SUBLW | kk | Subtract W from literal | WREG := kk - WREG |
| TRIS | r | Tristate port r (1) | I/O control reg r := WREG |
| XORLW | kk | Exclusive OR literal and W | WREG := kk XOR WREG |
|